? semiconductor components industries, llc, 2002 february, 2002 rev. 4 1 publication order number: cs8321/d cs8321 micropower 5.0 v, 150 ma low dropout linear regulator the cs8321 is a precision 5.0 v micropower voltage regulator with very low quiescent current (140 m a typ at 1.0 ma load). the 5.0 v output is accurate within 2% and supplies 150 ma of load current with a typical dropout voltage of only 300 mv. this combination of low quiescent current and outstanding regulator performance makes the cs8321 ideal for any battery operated equipment. the regulator is protected against reverse battery and short circuit conditions. the device can withstand 45 v load dump transients making it suitable for use in automotive environments. features ? 5.0 v 2% output ? low 140 m a (typ) quiescent current ? 150 ma output current capability ? fault protection 15 v reverse voltage output current limit ? low reverse current (output to input) figure 1. block diagram v in v out v out sense* gnd bandgap reference + current source (circuit bias) current limit sense error amplifier q p q n r r1 r2 *lead shorted to v out in 3pin applications r1 http://onsemi.com a = assembly location wl, l = wafer lot yy, y = year ww, w = work week marking diagrams d 2 pak 3pin dp suffix case 418e to220 three lead t suffix case 221a 1 2 3 pin 1. v in 2. gnd 3. v out cs8321 awlyww 1 d 2 pak cs8321 awlyww 1 to220 device package shipping ordering information* cs8321yt3 to220 three lead 50 units/rail cs8321ydp3 d 2 pak, 3pin 50 units/rail cs8321ydpr3 d 2 pak, 3pin 750 tape & reel *contact your local sales representative for so16, dip16, so8, and dip8 package options. 1 2 3
cs8321 http://onsemi.com 2 absolute maximum ratings* rating value unit transient input voltage 15, 45 v output current internally limited esd susceptibility (human body model) 2.0 kv junction temperature 40 to 150 c storage temperature 65 to 150 c lead temperature soldering wave solder (through hole styles only) note 1 reflow (smd styles only) note 2 260 peak 230 peak c c 1. 10 seconds max. 2. 60 seconds max above 183 c *the maximum package power dissipation must be observed. electrical characteristics (6.0 v < v in < 26 v, i out = 1.0 ma, 40 c t a 125 c, 40 c t j 150 c; unless otherwise specified.) characteristic test conditions min typ max unit output stage output voltage, v out 9.0 v < v in 16 v, 100 ma i out 150 ma 4.9 5.0 5.1 v dropout voltage (v in v out ) i out = 150 ma, 40 c t a 85 c i out = 150 ma, t a = 125 c 0.3 0.5 0.6 v v quiescent current, (i q ) i out = 1.0 ma @ v in = 13 v i out < 50 ma @ v in = 13 v i out < 150 ma @ v in = 13 v 4.0 15 200 6.0 25 m a ma ma load regulation v in = 14 v, 100 m a < i out < 150 ma 5.0 50 mv line regulation 6.0 v v 26 v, i out = 1.0 ma 5.0 50 mv ripple rejection 7.0 v in 17 v, i out = 150 ma, f = 120 hz 60 75 db current limit 175 250 ma short circuit output current v out = 0 v 60 200 ma reverse current v out = 5.0 v, v in = 0 v 140 200 m a package pin description package pin # to220 d 2 pak pin symbol function 1 1 v in input voltage. 2 2 gnd ground. all gnd leads must be connected to ground. 3 3 v out 5.0 v, 2%, 150 ma output.
cs8321 http://onsemi.com 3 circuit description and application notes voltage reference and output circuitry the cs8321 is a series pass voltage regulator. it consists of an error amplifier, bandgap voltage reference, pnp pass transistor with antisaturation control, and current limit. as the voltage at the input, v in , is increased (figure 1), q n is forward biased via r. q n provides base drive for q p . as q p becomes forward biased, the output voltage, v out , begins to rise as q p 's output current charges the output capacitor. once v out rises to a certain level, the error amplifier becomes biased and provides the appropriate amount of base current to q p . the error amplifier monitors the scaled output voltage via an internal voltage divider, r1 and r2, and compares it to the bandgap voltage reference. the error amplifier's output is a current which is equal to the error amplifier's differential input voltage times its transconductance. therefore, the error amplifier varies the base drive current to q n , which provides bias to q p , based on the difference between the reference voltage and the scaled output voltage, v out . antisaturation protection an antisaturation control circuit has also been added to prevent the pass transistor from going into deep saturation, which would cause excessive power dissipation due to large bias currents lost to the substrate via a parasitic pnp transistor, as shown in figure 2. figure 2. the parasitic pnp transistor which is part of the pass transistor (q p ) structure v out v in q p q parasitic substrate current limit limit the output stage is protected against short circuit conditions. as shown in figure 3, the output current will fold back when the faulted load is continually increased. this technique has been incorporated to limit the total power dissipation across the device during a short circuit condition, since the device does not contain overtemperature shutdown. stability considerations the output or compensation capacitor helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. figure 3. typical current limit and fold back waveform 0.0 0.0 output voltage 0.34257 load current 0.30831 0.27405 0.23980 0.20554 0.17128 0.13703 0.10277 0.06851 0.03426 0.51 1.02 1.52 2.03 2.54 3.05 3.56 4.06 4.57 5.08 curve will vary with temperature and process variation. the capacitor value and type should be based on cost, availability, size and temperature constraints. a tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero esr can cause instability. the aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (25 c to 40 c), both the value and esr of the capacitor will vary considerably. the capacitor manufacturers data sheet usually provides this information. the value for the output capacitor c out shown in figure 4 should work for most applications, however it is not necessarily the best solution. figure 4. test and application circuit showing output compensation cs8321 v in c in * 0.1 m f v out v out sense2 c out ** 0.1 m f *c in required if regulator is located far from the power supply filter. **c out required for stability. capacitor must operate at minimum temperature expected. 2pin internally shorted to v out in 3pin applications. to determine an acceptable value for c out for a particular application, start with a tantalum capacitor of the
cs8321 http://onsemi.com 4 recommended value and work towards a less expensive alternative part. step 1: place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. a decade box connected in series with the capacitor will simulate the higher esr of an aluminum capacitor. leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. step 2: with the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. if no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. step 3: increase the esr of the capacitor from zero using the decade box and vary the load current until oscillations appear. record the values of load current and esr that cause the greatest oscillation. this represents the worst case load conditions for the regulator at low temperature. step 4: maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. this point represents the worst case input voltage conditions. step 5: if the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. a smaller capacitor will usually cost less and occupy less board space. if the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next lar ger standard capacitor value. step 6: test the load transient response by switching in various loads at several frequencies to simulate its real working environment. vary the esr to reduce ringing. step 7: raise the temperature to the highest specified operating temperature. v ary the load current as instructed in step 5 to test for any oscillations. once the minimum capacitor value with the maximum esr is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. most good quality aluminum electrolytic capacitors have a tolerance of 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. the esr of the capacitor should be less than 50% of the maximum allowable esr found in step 3 above. calculating power dissipation in a single output linear regulator the maximum power dissipation for a single output regulator (figure 5) is: p d(max) ( v in(max) v out(min) ) i out(max) v in(max) i q (1) where: v in(max) is the maximum input voltage, v out(min) is the minimum output voltage, i out(max) is the maximum output current for the application, and i q is the quiescent current the regulator consumes at i out(max) . once the value of p d(max) is known, the maximum permissible value of r q ja can be calculated: r ja 150 c t a p d (2) the value of r q ja can then be compared with those in the package section of the data sheet. those packages with r q ja 's less than the calculated value in equation 2 will keep the die temperature below 150 c. in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heatsink will be required. figure 5. single output regulator with key performance parameters labeled cs8321 v in v out i in i out i q heatsinks a heatsink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r q ja : r ja r jc r cs r sa (3) where: r q jc = the junctiontocase thermal resistance, r q cs = the casetoheatsink thermal resistance, and r q sa = the heatsinktoambient thermal resistance. r q jc appears in the package section of the data sheet. like r q ja , it too is a function of package type. r q cs and r q sa are functions of the package type, heatsink and the interface between them. these values appear in heatsink data sheets of heatsink manufacturers.
cs8321 http://onsemi.com 5 package dimensions to220 three lead t suffix case 221a08 issue aa notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. a k l g d n h q f 123 4 t seating plane s r j u t c 3 pl b y m b m 0.25 (0.010) y dim min max min max millimeters inches a 0.560 0.625 14.23 15.87 b 0.380 0.420 9.66 10.66 c 0.140 0.190 3.56 4.82 d 0.025 0.035 0.64 0.89 f 0.139 0.155 3.53 3.93 g 0.100 bsc 2.54 bsc h --- 0.280 --- 7.11 j 0.012 0.045 0.31 1.14 k 0.500 0.580 12.70 14.73 l 0.045 0.060 1.15 1.52 n 0.200 bsc 5.08 bsc q 0.100 0.135 2.54 3.42 r 0.080 0.115 2.04 2.92 s 0.020 0.055 0.51 1.39 t 0.235 0.255 5.97 6.47 u 0.000 0.050 0.00 1.27 v v 0.045 --- 1.15 --- d 2 pak 3pin dp suffix case 418e01 issue o t dim min max min max millimeters inches a 0.326 0.336 8.28 8.53 b 0.396 0.406 10.05 10.31 c 0.170 0.180 4.31 4.57 d 0.026 0.036 0.66 0.91 e 0.045 0.055 1.14 1.40 f 0.090 0.110 2.29 2.79 g 0.100 bsc 2.54 bsc h 0.098 0.108 2.49 2.74 j 0.018 0.025 0.46 0.64 k 0.204 0.214 5.18 5.44 m 0.055 0.066 1.40 1.68 n 0.000 0.004 0.00 0.10 notes: 1. dimensions and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. b n a k m e c seating plane f h j d 3 pl g t m 0.13 (0.005) m b 123 4 l l 0.045 0.055 1.14 1.40 package thermal data
cs8321 http://onsemi.com 6 package thermal data parameter to220 d 2 pak unit r q jc typical 3.5 1.0* c/w r q ja typical 50 10502 c/w *depending on die area. 2depending on thermal properties of substrate. r q ja = r q jc + r q ca .
cs8321 http://onsemi.com 7 notes
cs8321 http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. cs8321/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
|
